#ifndef __CIPHER_REG_H__
#define __CIPHER_REG_H__
#include "types.h"
#include "base.h"

#define CIPHER_SPACC_CRG_ADDR_PHY               (0xf8a223c0)
#define CIPHER_SM4_REG_BASE_ADDR_PHY            (0xF8A208C4)

/* CIPHER register */
#define REG_CIPHER_BASE             (0xf9a00000)             /* 0xf9a0_0000 */

/***************************** Macro Definition ******************************/
#define CHAN0_CIPHER_IV                         (REG_CIPHER_BASE + 0x0000)
#define CHANn_CIPHER_IVOUT(id)                  (REG_CIPHER_BASE + 0x0000 + (id)*0x10)
#define CHAN0_CIPHER_DOUT                       (REG_CIPHER_BASE + 0x0080)
#define CIPHER_KEY(id)                          (REG_CIPHER_BASE + 0x0100 + (id)*0x20)
#define SM1_SK(id)                              (REG_CIPHER_BASE + 0x0200 + (id)*0x10)
#define ODD_EVEN_KEY_SEL                        (REG_CIPHER_BASE + 0x0290)
#define HDCP_MODE_CTRL                          (REG_CIPHER_BASE + 0x0300)
#define SEC_CHN_CFG                             (REG_CIPHER_BASE + 0x0304)
#define CALC_ERR                                (REG_CIPHER_BASE + 0x0320)
#define CHAN0_CIPHER_CTRL                       (REG_CIPHER_BASE + 0x0400)
#define CIPHER_INT_STATUS                       (REG_CIPHER_BASE + 0x0404)
#define CIPHER_INT_EN                           (REG_CIPHER_BASE + 0x0408)
#define CIPHER_INT_RAW                          (REG_CIPHER_BASE + 0x040c)
#define CIPHER_IN_SMMU_EN                       (REG_CIPHER_BASE + 0x0410)
#define OUT_SMMU_EN                             (REG_CIPHER_BASE + 0x0414)
#define CHAN0_CIPHER_DIN                        (REG_CIPHER_BASE + 0x0420)
#define NORM_SMMU_START_ADDR                    (REG_CIPHER_BASE + 0x0440)
#define SEC_SMMU_START_ADDR                     (REG_CIPHER_BASE + 0x0444)
#define CHANn_CIPHER_CTRL(id)                   (REG_CIPHER_BASE + 0x0400 + (id)*0x80)
#define CHANn_CIPHER_IN_NODE_CFG(id)            (REG_CIPHER_BASE + 0x0404 + (id)*0x80)
#define CHANn_CIPHER_IN_NODE_START_ADDR(id)     (REG_CIPHER_BASE+0x0408+(id)*0x80)
#define CHANn_CIPHER_IN_BUF_RPTR(id)            (REG_CIPHER_BASE+0x040C+(id)*0x80)
#define CHANn_CIPHER_OUT_NODE_CFG(id)           (REG_CIPHER_BASE + 0x0430 + (id)*0x80)
#define CHANn_CIPHER_OUT_NODE_START_ADDR(id)    (REG_CIPHER_BASE+0x0434+(id)*0x80)
#define CHANn_CIPHER_OUT_BUF_RPTR(id)           (REG_CIPHER_BASE+0x0438+(id)*0x80)

#define CHAN0_HASH_CTRL                         (REG_CIPHER_BASE + 0x0800)
#define HASH_INT_STATUS                         (REG_CIPHER_BASE + 0x0804)
#define HASH_INT_EN                             (REG_CIPHER_BASE + 0x0808)
#define HASH_INT_RAW                            (REG_CIPHER_BASE + 0x080C)
#define HASH_IN_SMMU_EN                         (REG_CIPHER_BASE + 0x0810)
#define CHAN0_HASH_DAT_IN                       (REG_CIPHER_BASE + 0x0818)
#define CHAN0_HASH_TOTAL_DAT_LEN                (REG_CIPHER_BASE + 0x081C)
#define CHANn_HASH_CTRL(id)                     (REG_CIPHER_BASE + 0x0800 + (id)*0x80)
#define CHANn_HASH_IN_NODE_CFG(id)              (REG_CIPHER_BASE + 0x0804 + (id)*0x80)
#define CHANn_HASH_IN_NODE_START_ADDR(id)       (REG_CIPHER_BASE + 0x0808 + (id)*0x80)
#define CHANn_HASH_IN_BUF_RPTR(id)              (REG_CIPHER_BASE + 0x080C + (id)*0x80)
#define CHANn_HASH_STATE_VAL(id)                (REG_CIPHER_BASE + 0x0340 + (id)*0x08)
#define CHANn_HASH_STATE_VAL_ADDR(id)           (REG_CIPHER_BASE + 0x0344 + (id)*0x08)

#define  SM2_REG_BASE_ADDR              (0xF9A38000)
#define  SM2_CRG_ADDR_PHY               (0xF8A80060)//(0xf8a223c4)
#define  SM2_REG_BUSY                   (SM2_REG_BASE_ADDR + 0x00)
#define  SM2_REG_WORK_MODE              (SM2_REG_BASE_ADDR + 0x04)
#define  SM2_REG_STRAT                  (SM2_REG_BASE_ADDR + 0x08)
#define  SM2_REG_DEBUG_EN               (SM2_REG_BASE_ADDR + 0x10)
#define  SM2_REG_RNG_OPTION             (SM2_REG_BASE_ADDR + 0x14)
#define  SM2_REG_INT_ENABLE             (SM2_REG_BASE_ADDR + 0x20)
#define  SM2_REG_INT_STATUS             (SM2_REG_BASE_ADDR + 0x24)
#define  SM2_REG_NOMASK_STATUS          (SM2_REG_BASE_ADDR + 0x28)
#define  SM2_REG_RESULT_FLAG            (SM2_REG_BASE_ADDR + 0x40)
#define  SM2_REG_FAILURE_FLAGS          (SM2_REG_BASE_ADDR + 0x44)
#define  SM2_REG_RRAM_CTRL_CFG          (SM2_REG_BASE_ADDR + 0x6c)
#define  SM2_REG_WP_L                   (SM2_REG_BASE_ADDR + 0x80)
#define  SM2_REG_WP_H                   (SM2_REG_BASE_ADDR + 0x84)
#define  SM2_REG_OTP_KEY_SEL_EN         (SM2_REG_BASE_ADDR + 0x88)
#define  SM2_REG_KEY_RANDOM             (SM2_REG_BASE_ADDR + 0x8c)
#define  SM2_REG_KEY_CRC                (SM2_REG_BASE_ADDR + 0x90)
#define  SM2_REG_KEY_CFG                (SM2_REG_BASE_ADDR + 0x9c)
#define  SM2_REG_KEY_RANDOM_A           (SM2_REG_BASE_ADDR + 0x100)
#define  SM2_REG_MRAM                   (SM2_REG_BASE_ADDR + 0x200)
#define  SM2_REG_NRAM                   (SM2_REG_BASE_ADDR + 0x600)
#define  SM2_REG_KRAM                   (SM2_REG_BASE_ADDR + 0xa00)
#define  SM2_REG_RRAM                   (SM2_REG_BASE_ADDR + 0xe00)

#define CIPHER_RSA_CRG_ADDR_PHY             0xF8A80060//(0xf8a223c4)
#define SEC_RSA_BUSY_REG                (RSA_REG_BASE + 0x50)
#define SEC_RSA_MOD_REG                 (RSA_REG_BASE + 0x54)
#define SEC_RSA_WSEC_REG                (RSA_REG_BASE + 0x58)
#define SEC_RSA_WDAT_REG                (RSA_REG_BASE + 0x5c)
#define SEC_RSA_RPKT_REG                (RSA_REG_BASE + 0x60)
#define SEC_RSA_RRSLT_REG               (RSA_REG_BASE + 0x64)
#define SEC_RSA_START_REG               (RSA_REG_BASE + 0x68)
#define SEC_RSA_ADDR_REG                (RSA_REG_BASE + 0x6C)
#define SEC_RSA_ERROR_REG               (RSA_REG_BASE + 0x70)
#define SEC_RSA_CRC16_REG               (RSA_REG_BASE + 0x74)
#define SEC_RSA_KEY_RANDOM_1            (RSA_REG_BASE + 0x7c)
#define SEC_RSA_INT_EN                  (RSA_REG_BASE + 0x80)
#define SEC_RSA_INT_STATUS              (RSA_REG_BASE + 0x84)
#define SEC_RSA_INT_RAW                 (RSA_REG_BASE + 0x88)
#define SEC_RSA_INT_ERR_CLR             (RSA_REG_BASE + 0x8c)
#define SEC_RSA_KEY_RANDOM_2            (RSA_REG_BASE + 0x94)

#define ADDR_MCU_LPDS_HASH_NODE         (ADDR_MCU_LPDS_START + 0x340)
#define ADDR_MCU_LPDS_HASH_PADDING      (ADDR_MCU_LPDS_START + 0x380)

#endif
